Robust Subthreshold Circuit Designing Using Sub-threshold Source Coupled Logic (STSCL)

The demand for building ultra low power circuit emerges as a challenge in recent years. This demand is due to the fast growth in battery operated wearable computing systems and implantable medical instruments. The design challenges in such systems are; low sensitivity to supply voltage variation and independence in performance with respect to power supply. Furthermore, these challenges are to be mitigated with the objective of ultra low power consumption. Subthreshold regime of operation of the devices is preferred these days which satisfies the need of ultra low power operation. The devices are operated at subthreshold regime when the supply voltages are scaled below the threshold voltage (VT) of the devices. The complementary metal oxide semiconductor (CMOS) logics are preferred conventionally for minimum energy consumption, but with scaling down of technology the leakage currents become dominant in these logics. The CMOS logic requires careful control of supply voltage since both the power consumption and speed of operation depends upon supply voltage. Furthermore, the CMOS logic does not satisfy the need of substrate and supply noise immunity. This leads to the evolution of Sub-threshold source coupled logic (STSCL) which not only mitigate the noises but also proves to consume few picoWatts of power at subthreshold. This power consumption is much lower as compared to the subthreshold leakage of static CMOS logic. These superior properties of STSCL makes it suitable candidate for implementing ultra-low-power systems in modern nano meter scale technologies. In this paper we have investigated all these properties of STSCL logic and its few applications. It is concluded that STSCL not only has comparable or even better power-delay performance but also has more robust in its performance at both analog and digital domain. Consequently, the STSCL is a promising candidate for designing ultra low power gadgets.